The size of the market for nonvolatile semiconductor memories has been increasing. Flash memories are one of semiconductor memories utilizing floating gate transistors to achieve nonvolatility of data.
In a conventional flash memory, data erasure is performed on a physical block basis, the physical block including a plurality of pages, and reading and writing of data are performed page by page. Even if a random write request is received, data write operation is controlled such that data is written in all erased pages of the physical block sequentially from the first page. To such a flash memory, sequential write access is controlled in accordance with mapping from logical (virtual) pages to physical pages. Each of the pages includes a data area for storing data and a redundant area for storing data management information. The redundant area of each page stores a logical page number (address) associated with data written in the data area of the same page (see Patent Publication 1) as data management information.
According to another conventional technique, when it is requested to rewrite or additionally write the pages in a single physical block of a flash memory which requires sequential write, new page data is written in a new erased physical block sequentially from the first page, and then data previously written in the pages of the physical block before updating is transferred to the rest of the pages in the new physical block. A page offset, which is the difference between the logical page number and the physical page number, is stored in the redundant areas of the flash memory. Data management information contained in the redundant areas of the pages includes a logical address corresponding to the physical page to which it belongs, a flag indicating whether or not the page is blank, a flag indicating whether the data written in the page is enabled or disabled and information for detecting an error of the data. The correspondence between the logical block address and the physical block address is controlled by an address conversion table (see Patent Publication 2).    Patent Publication 1: International Patent Publication No. 2003/030180 (pamphlet)    Patent Publication 2: International Patent Publication No. 2004/021191 (pamphlet)